Enum riscy::Instruction

source ·

pub enum Instruction {
Show 42 variants    Beq {
        rs1: Reg,
        rs2: Reg,
        imm: ImmB,
    },
    Bne {
        rs1: Reg,
        rs2: Reg,
        imm: ImmB,
    },
    Blt {
        rs1: Reg,
        rs2: Reg,
        imm: ImmB,
    },
    Bge {
        rs1: Reg,
        rs2: Reg,
        imm: ImmB,
    },
    Bltu {
        rs1: Reg,
        rs2: Reg,
        imm: ImmB,
    },
    Bgeu {
        rs1: Reg,
        rs2: Reg,
        imm: ImmB,
    },
    Jalr {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Jal {
        rd: Reg,
        imm: ImmJ,
    },
    Lui {
        rd: Reg,
        imm: ImmU,
    },
    Auipc {
        rd: Reg,
        imm: ImmU,
    },
    Addi {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Slti {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Sltiu {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Xori {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Ori {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Andi {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Slli {
        rd: Reg,
        rs1: Reg,
        shamt: ImmI,
    },
    Srli {
        rd: Reg,
        rs1: Reg,
        shamt: ImmI,
    },
    Srai {
        rd: Reg,
        rs1: Reg,
        shamt: ImmI,
    },
    Add {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sub {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sll {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Slt {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sltu {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Xor {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Srl {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Sra {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Or {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    And {
        rd: Reg,
        rs1: Reg,
        rs2: Reg,
    },
    Lb {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Lh {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Lw {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Lbu {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Lhu {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Lwu {
        rd: Reg,
        rs1: Reg,
        imm: ImmI,
    },
    Sb {
        imm: ImmS,
        rs1: Reg,
        rs2: Reg,
    },
    Sh {
        imm: ImmS,
        rs1: Reg,
        rs2: Reg,
    },
    Sw {
        imm: ImmS,
        rs1: Reg,
        rs2: Reg,
    },
    Fence {
        rd: Reg,
    },
    FenceI {
        rd: Reg,
    },
    ECall,
    EBreak,
}

Expand description

A struct for representing a fully decoded r32i instruction. Each variant matches an assembly instruction.

Note that pseudo-instructions, such as li (load immediate) or mv (move), are short-hands used by RISC-V assemblers for short, common sequences of basic instructions. This struct only the basic instructions themselves, and so it does not list any pseudo-instructions.